1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory.
2. Description of the Related Art
In a conventional dynamic random access memory (DRAM), a memory cell consists of one field effect transistor and a capacitor. In the field of such a one transistor-one capacitor memory cell, various techniques for reducing the size of the cell have been proposed in order to enhance the integration degree. However, a transistor must be formed vertically, which is technically difficult; there arise problems such as that electrical interference between adjacent memory cells is significant; and there are difficulties in the production technique of processing, film formation, and the like. Therefore, it is not easy to realize practical application of such techniques.
By contrast, several proposals for a DRAM in which one transistor is formed as a memory cell without using a capacitor to reduce the cell size, or a so-called capacitor-less DRAM, have been made (for example, see T. Ohsawa, et al., IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, pp. 1510-1522 (2002)).
Ohsawa, et al. has disclosed a capacitor-less DRAM having a structure in which a channel region is formed on a substrate having the SOI structure, source/drain regions are formed on the both sides of the channel region, and a gate electrode is formed on the channel region via a gate insulating film.
The DRAM dynamically stores a first data state (e.g., data “1”), which has a first threshold voltage and in which excessive majority carriers are retained in the channel region, or a second data state (e.g., data “0”) which has a second threshold voltage and in which excessive majority carriers in the channel region are emitted.
To inject majority carriers into the channel region, the transistor is operated and majority carriers generated by causing impact ionization in the vicinity of a drain junction are retained in the channel region. To emit majority carriers from the channel region, a potential of the same sign as the majority carriers is applied to the gate electrode, and a potential of the sign opposite to the majority carriers is applied to the drain region, thereby to apply a forward bias to a pn junction between the drain region and the channel region.
By contrast, reading of information uses variation of the threshold of the transistor depending on the presence or absence of majority carriers in the channel region. For example, a drain current in the case where a reading voltage between the thresholds of the first and second data states is applied is detected, and it is judged whether the information is in the first data state or in the second data state.